Author:
Ajane Avinash,Furth Paul M.,Johnson Eric E.,Subramanyam Rashmi Lakkur
Cited by
11 articles.
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1. Optimized Parallel Architecture for a Constant-Time Synchronous Binary Counter with Minimal Clock Period;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. 64-Bit High Speed Counter with Galois LFSR;2024 International Conference on Circuit, Systems and Communication (ICCSC);2024-06-28
3. Constant-Time Synchronous Binary Counter with Minimal Clock Period;2024 5th International Conference on Recent Trends in Computer Science and Technology (ICRTCST);2024-04-09
4. Streamlined Synchronous Binary Counter with Minimized Clock Period;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19
5. Programmable Feedback Shift Register;Circuits, Systems, and Signal Processing;2023-03-11