Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization

Author:

Horeni Mark1,Taheri Pooria1,Tsai Po-An2,Parashar Angshuman2,Emer Joel3,Joshi Siddharth1

Affiliation:

1. University of Notre Dame,Computer Science and Engineering,Notre Dame,IN,USA

2. NVIDIA,Westford,MA,USA

3. MIT / NVIDIA,Cambridge,MA,USA

Funder

Semiconductor Research Corporation

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators;Proceedings of the 21st ACM International Conference on Computing Frontiers;2024-05-07

3. Architecture-Level Modeling of Photonic Deep Neural Network Accelerators;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

4. Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming;Proceedings of the 20th ACM International Conference on Computing Frontiers;2023-05-09

5. Demystifying Map Space Exploration for NPUs;2022 IEEE International Symposium on Workload Characterization (IISWC);2022-11

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