FPGA Implementation of CNN Accelerator with Pruning for ADAS Applications-Reference-Cited by-同舟云学术

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FPGA Implementation of CNN Accelerator with Pruning for ADAS Applications

Published:2024-04-05 Issue: Volume:11 Page:1-6
ISSN:
Container-title:2024 IEEE 9th International Conference for Convergence in Technology (I2CT)
language:
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Author:

Jose Aimy¹,Alense K. T.²,Gijo Liya²,Jacob Jobymol¹

Affiliation:

1. Thrikkakara APJ Abdul Kalam Technological University,Department of Electronics Engineering Model Engineering College,Kerala,India

2. Poonjar APJ Abdul Kalam Technological University,Department of Electronics Engineering College of Engineering,Kerala,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10543249/10543223/10544357.pdf?arnumber=10544357

Reference16 articles.

1. Performance Optimisation of Parallelized ADAS Applications in FPGA-GPU Heterogeneous Systems: A Case Study With Lane Detection

2. A Low-Cost Fully Integer-Based CNN Accelerator on FPGA for Real-Time Traffic Sign Recognition

3. Accelerating Convolutional Neural Network With FFT on Embedded Hardware

4. FPGA-based Acceleration for Convolutional Neural Networks on PYNQ-Z2;Huynh,2022

5. FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements

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