High speed efficient FPGA implementation of pipelined AES S-Box-Reference-Cited by-同舟云学术

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High speed efficient FPGA implementation of pipelined AES S-Box

Published:2016-10 Issue: Volume: Page:
ISSN:
Container-title:2016 4th IEEE International Colloquium on Information Science and Technology (CiSt)
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Author:

Oukili Soufiane,Bri Seddik,Kumar A. V. Senthil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7786012/7804840/07805015.pdf?arnumber=7805015

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration;2024 International Telecommunications Conference (ITC-Egypt);2024-07-22

2. A Novel Approach to AES S-BOX and Inverse S-BOX Design on FPGA Devices;2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2023-12-18

3. Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography;2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS);2021-04-21

4. An Efficient AES with Custom Configurable Encryption Algorithm Using Dynamic Keys for Secure Data Communication in Networks;International Conference on Mobile Computing and Sustainable Informatics;2020-12-01

5. High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications;IET Computers & Digital Techniques;2020-09-10

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