A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration-Reference-Cited by-同舟云学术

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A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration

Published:2009-09 Issue: Volume: Page:
ISSN:
Container-title:2009 IEEE Energy Conversion Congress and Exposition
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Author:

Bergveld H.J.,Nowak K.,Karadi R.,Iochem S.,Ferreira J.,Ledain S.,Pieraerts E.,Pommier M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5305884/5315930/05316334.pdf?arnumber=5316334

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