Substrate engineering for improved transient breakdown voltage in SOI lateral power MOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx5/55/34771/01661728.pdf?arnumber=1661728
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer;Micromachines;2023-04-20
2. Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage;IEEE Access;2020
3. A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage;Semiconductor Science and Technology;2011-07-06
4. Duration of the High Breakdown Voltage Phase in Deep Depletion SOI LDMOS;IEEE Electron Device Letters;2007-08
5. Limits and application of the newly proposed deep-depletion SOI LDMOS;IET Circuits, Devices & Systems;2007
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