Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer
Author:
Affiliation:
1. Intel Technology India Pvt Ltd,Bengaluru,India
2. KLE Technological University,Department of Electronics and Communication,Hubli,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9687621/9687623/09687738.pdf?arnumber=9687738
Reference10 articles.
1. Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique
2. Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors
3. 40-nm $2\times \text{vdd}$ Digital Output Buffer Design With DDR4-Compliant Slew Rate;wang;Asia Pacific Conference on Circuits and Systems (APCCAS),2018
4. A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit
5. Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a $0.13- \mu \mathrm{m}$ CMOS technology;chuang;IEEE International Symposium on Circuits and Systems,2004
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