SADP etch process development using PR core for sub 17nm DRAM

Author:

Xu Li Tian1,Zhang Shuai2,Li Ling Feng1,Liu Hao1,Huang Xin Wen2,Chen Ying Yi2,Su Xian Wen2,Guo Zhong Ning2,Xiu Chun Yu2,Mu Tian Lei2,Lin Bing Hui2,He Zhong Yi1,Zhou Qing Jun1

Affiliation:

1. Beijing NAURA Microelectronics Equipment Co. Ltd, Beijing Economic-Technological Development Area,Beijing City,China

2. ChangXin Memory Technologies, Inc. Ltd, Economic and Technological Development Area,Hefei City,China

Publisher

IEEE

Reference8 articles.

1. Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme;mohanty;Proc of SPIE,0

2. SAQP Pitch Walking Improvement Path Finding by Simulation;yang;2019 International Symposium on Dry Process (DPS),0

3. Self-aligned Quadruple Patterning Integration using spacer on spacer pitch splitting at the resist level for sub 32nm pitch applications;raley;Proc of SPIE,0

4. Optimization of the CD uniformity (CDU) in silicon oxide spacer process for 5nm FIN SAQP process flow;qingqing;2020 China Semiconductor Technology International Conference (CSTIC),0

5. An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

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