Improving the Device Performance of LDMOS Through the Optimization of Structure
Author:
Affiliation:
1. Shanghai Huali Microelectronics Corporation,Shanghai,China,201203
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9856647/9856709/09856800.pdf?arnumber=9856800
Reference6 articles.
1. Electron trapping and interface trap generation in drain extended pMOS transistors
2. High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC
3. 0.18µm 100V-rated BCD with large area power LDMOS with ultra-low effective specific resistance;cha;Proc 5th Int Symp Power Semiconductor Devices and ICs (ISPSD),2016
4. On the static performance of the RESURF LDMOSFETS for power ICs
5. Power efficient charge pump in deep submicron standard cmos technology
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. ESD-ability Analysis of High Voltage nLDMOSs with the Drain-side Parasitic Schottky/Embedded STI;2022 IEEE 4th Eurasia Conference on IOT, Communication and Engineering (ECICE);2022-10-28
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