Extended RISC-V hardware architecture for future digital communication systems

Author:

Tourres Mael,Chavet Cyrille,Le Gal Bertrand,Crenne Jeremie,Coussy Philippe

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Automating application-driven customization of ASIPs: A survey;Journal of Systems Architecture;2024-03

2. Domain-Specific FPGA-Based Digital Acquisition System for Hardware Accelerators Integration;Bulletin of the Polytechnic Institute of Iași. Electrical Engineering, Power Engineering, Electronics Section;2023-06-01

3. Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool;Micromachines;2023-01-12

4. RISC-V Instruction Set Architecture Extensions: A Survey;IEEE Access;2023

5. Communications Signal Processing Using RISC-V Vector Extension;2022 International Wireless Communications and Mobile Computing (IWCMC);2022-05-30

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