A VLSI design for a trace-back Viterbi decoder
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/26/3699/00135732.pdf?arnumber=135732
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1. Design Architecture of a 2-D Separable Iterative Soft-Output Viterbi Detector;IEEE Transactions on Magnetics;2016-05
2. A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA;2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID);2016-01
3. Low-power multi-standard Viterbi decoder for wireless communication applications;International Journal of Electronics Letters;2015-04-02
4. An efficient sliding window algorithm using adaptive-length guard window for turbo decoders;Journal of Communications and Networks;2012-04
5. Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE;VLSI-SoC: Forward-Looking Trends in IC and Systems Design;2012
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