An Area Efficient Low-Power mmWave PRBS Generator in FDSOI
Author:
Affiliation:
1. Institute for Electronics Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg,Germany
2. Institute for CMOS Design, Technische Universität,Braunschweig,Germany
Funder
Federal Ministry of Education and Research (BMBF)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9865233/9865240/09865592.pdf?arnumber=9865592
Reference6 articles.
1. A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output
2. A Low-Power D-type Flip-flop with Active Inductor and Forward Body Biasing Techniques in 40-nm CMOS
3. A 0.35 mW 70 GHz Divide-by-4 TSPC Frequency Divider on 22 nm FD-SOI CMOS Technology
4. A 1-pJ/bit 80-Gb/s $2^{15}-1$ PRBS Generator With a Modified Cherry–Hooper Output Driver
5. A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator
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