Designing High-Performance Interconnection Networks with Host-Switch Graphs-Reference-Cited by-同舟云学术

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Designing High-Performance Interconnection Networks with Host-Switch Graphs

Published:2019-02-01 Issue:2 Volume:30 Page:315-330
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Yasudo Ryota^ORCID,Koibuchi Michihiro,Nakano Koji^ORCID,Matsutani Hiroki,Amano Hideharu

Funder

KAKENHI

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx7/71/8613032/08428449.pdf?arnumber=8428449

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimization Algorithm with Automatic Adjustment of the Number of Switches in the Order/Radix Problem;IEICE Transactions on Information and Systems;2023-12-01

2. Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints;2023 Eleventh International Symposium on Computing and Networking (CANDAR);2023-11-28

3. Realizing Optimal All-to-All Personalized Communication Using Butterfly-Based Networks;IEEE Access;2023

4. Graph optimization algorithm using symmetry and host bias for low-latency indirect network;Parallel Computing;2022-12

5. Edge-Based Heuristics for Optimizing Shortcut-Augmented Topologies for HPC Interconnects;Electronics;2022-09-03

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