Bi-level reconfigurations of fault tolerant arrays

Author:

Melhem R.G.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement;Transactions on Computational Science XXVII;2016

2. Optimal reconfiguration algorithms for real-time fault-tolerant processor arrays;IEEE Transactions on Parallel and Distributed Systems;1995-05

3. Channel Multiplexing in Fault-Tolerant Modular Multiprocessors;Journal of Parallel and Distributed Computing;1995-02

4. Average-case scalable on-line algorithms for fault replacement;Information Processing Letters;1994-11

5. Computational arrays with flexible redundancy;IEEE Transactions on Computers;1994-04

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