An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder-Reference-Cited by-同舟云学术

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An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Published:2014-12 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE Visual Communications and Image Processing Conference
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Author:

Sun Heming,Zhou Dajiang,Zhu Jiayi,Kimura Shinji,Goto Satoshi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7041330/7051488/07051538.pdf?arnumber=7051538

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28

2. An Area-efficient Unified Transform Architecture for VVC;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

3. Approximated Reconfigurable Transform Architecture for VVC;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

4. Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC;Electronics;2021-03-05

5. A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard;IEEE Transactions on Circuits and Systems for Video Technology;2020-09

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