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Warpage Analysis of Fan-Out Panel-Level Packaging Using Equivalent CTE

  • Published:2020-03 Issue:1 Volume:20 Page:51-57
  • ISSN:1530-4388
  • Container-title:IEEE Transactions on Device and Materials Reliability
  • language:
  • Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Tsai C. H.,Liu S. W.,Chiang K. N.ORCID

Funder

Powertech Technology Inc

National Tsing HuaUniversity

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reduced warpage in semiconductor packages: Optimizing post-cure temperature profile considering cure shrinkage and viscoelasticity of epoxy molding compound;Materials & Design;2024-09

2. How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Warpage Estimation of Panel-Level Packaging by AI-assisted Design on Simulation;2024 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE);2024-04-07

4. Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-12

5. High‐Temperature Polymer‐Based Dielectrics for Advanced Electronic Packaging;High Temperature Polymer Dielectrics;2023-11-03
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