Double-Side Process and Reliability of Through-Silicon Vias for Passive Interposer Applications-Reference-Cited by-同舟云学术

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Double-Side Process and Reliability of Through-Silicon Vias for Passive Interposer Applications

Published:2014-12 Issue:4 Volume:14 Page:1041-1048
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Chen Qiao,Liu Xi,Sundaram Venkatesh,Sitaraman Suresh K.,Tummala Rao R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/7298/6971050/06915697.pdf?arnumber=6915697

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Liner Formation Strategy for Double-sided Through-silicon-via (TSV) Process;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

2. Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-01

3. Laminated process effect of high-density redistributed trace lines on the risk estimation of induced-stress failure for 3D-IC embedded interposer;Microsystem Technologies;2017-11-18

4. Modeling, Fabrication, and Reliability of Through Vias in Polycrystalline Silicon Panels;IEEE Transactions on Components, Packaging and Manufacturing Technology;2015-07

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