Quick Compact Model Development Through Slow Transient Simulation: An Alternative Approach to Table Models for Emerging Nanodevices
Author:
Affiliation:
1. TU Darmstadt,Integrated Electronic Systems Lab
Funder
Deutsche Forschungsgemeinschaft
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9841660/9841947/09842125.pdf?arnumber=9842125
Reference12 articles.
1. Reconfigurable Silicon Nanowire Transistors
2. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
3. Junction‐less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio‐frequency performance
4. From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI
5. MOS table models for circuit simulation
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1. Machine Learning-Based Compact Model Design for Reconfigurable FETs;IEEE Journal of the Electron Devices Society;2024
2. Generating Predictive Models for Emerging Semiconductor Devices;IEEE Journal of the Electron Devices Society;2024
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