The Effect of Sige Siconi Pre-Clean Time On Planner Logic Device Performance Study
Author:
Affiliation:
1. Semiconductor Manufacturing North China (Beijing) Corporation,Beijing,China,100176
2. Semiconductor Technology Innovation Center (Beijing) Corporation,Beijing,China,100176
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10219185/10219154/10219317.pdf?arnumber=10219317
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3. Mobility and Velocity Enhancement Effects of High Uniaxial Stress on Si (100) and (110) Substrates for Short-Channel pFETs
4. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application;chen;VLSI Symp Tech Dig,2004
5. A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology
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