Power Efficient Approximate Ternary Subtractor for Image Processing Applications-Reference-Cited by-同舟云学术

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Power Efficient Approximate Ternary Subtractor for Image Processing Applications

Published:2023-12-18 Issue: Volume:48 Page:127-130
ISSN:
Container-title:2023 IEEE International Symposium on Smart Electronic Systems (iSES)
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Author:

Tharuni Sangireddy¹,Reddy Basani Harshavardhan¹,Mamatha Bhukya¹,Kumar Uppugunduru Anil²,Ahmed Syed Ershad³,Veeramachaneni Sreehari¹

Affiliation:

1. Gokaraju Rangaraju Institute of Engineering Technology,Department of Electronics and Communication Engineering,Hyderabad,India

2. The ICFAI Foundation for Higher Education (Deemed to be University),Faculty of Science and Technology (IcfaiTech),Department of Electronics and Communication Engineering,Hyderabad,Telangana,India,501203

3. BITS Pilani Hyderabad Campus,Department of Electrical and Electronics Engineering,Hyderabad,Telangana,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10467041/10466793/10467066.pdf?arnumber=10467066

Reference12 articles.

1. Multiple-valued logic in VLSI: challenges and opportunities;Dubrova,1999

2. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

3. Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity

4. Low-Complexity Arithmetic Circuit Design in Carbon Nanotube Field Effect Transistor Technology

5. Hardware-efficient approx-imate multiplier architectures for media processing applications;Uppugunduru,2022

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