Optimization and Representation of Non-Slicing VLSI Floorplanning
Author:
Affiliation:
1. PSNA College of Engineering and Technology,Department of Electronics and Communication Engineering,Dindigul,India
2. Thiagarajar College of Engineering,Department of Computer Science and Engineering,Madurai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10275782/10275807/10276362.pdf?arnumber=10276362
Reference23 articles.
1. Module placement on BSG-structure and IC layout applications
2. Floorplanning using a tree representation;guo;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2001
3. A Modified SA Algorithm for VLSI floorplan;aravindaraj;International Journal of Scientific and Research Publications (IJSRP),2019
4. Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary
5. TCG-S: Orthogonal Coupling of<tex>$rm P^ast$</tex>-Admissible Representations for General Floorplans
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