Failure Analysis Methodology on Solder Bump Bridging Defects for 14nm Technology-Reference-Cited by-同舟云学术

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Failure Analysis Methodology on Solder Bump Bridging Defects for 14nm Technology

Published:2023-07-24 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
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Author:

Khoo Hsu Li¹,Ong Zhe Han¹

Affiliation:

1. Intel Malaysia sdn. bhd, Phase 4,Penang,Malaysia

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10248978/10248979/10249076.pdf?arnumber=10249076

Reference3 articles.

1. Intel’s Process Raodmap to 2025: with 4nm,3nm, 20A and 18A;cutress,0

2. Semiconductor Logic Technology in IBM

3. Design and Implementation of EMIB Testing on 2.5D FPGA Transceiver; 2016 IEEE 25th Asian Test Symposium (ATS);tan;2016 presented at 2016 IEEE 25th Asian Test Symposium (ATS),0

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