A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs

Author:

Siozios Kostas,Soudris Dimitrios

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Computer Science,Control and Systems Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area;Journal of Circuits, Systems and Computers;2017-03-08

2. A Customizable Framework for Application Implementation onto 3-D FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-11

3. Modular Placement for Interposer based Multi-FPGA Systems;Proceedings of the 26th edition on Great Lakes Symposium on VLSI;2016-05-18

4. Plug&Chip;ACM Transactions on Embedded Computing Systems;2014-12-15

5. A framework for rapid evaluation of heterogeneous 3-D NoC architectures;Microprocessors and Microsystems;2014-06

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