Author:
Chun Zheng,Yongjun Zhou,Xin Chen,Xiaoguang Guo
Cited by
3 articles.
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1. Accurate operation delay prediction for FPGA HLS using graph neural networks;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02
2. Latency estimation and optimization for DSP blocks in high level synthesis stage;AOPC 2017: 3D Measurement Technology for Intelligent Manufacturing;2017-10-24
3. Mapping for Maximum Performance on FPGA DSP Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-04