FinFET-Premised 1-Bit Comparator Design Using CPTL and DCVSPG Techniques-Reference-Cited by-同舟云学术

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FinFET-Premised 1-Bit Comparator Design Using CPTL and DCVSPG Techniques

Published:2023-02-10 Issue: Volume: Page:
ISSN:
Container-title:2023 11th International Conference on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON)
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Author:

Rajora Ricky¹,Sharma Kulbhushan¹,Sharma Anjali²,Gupta Lipika³

Affiliation:

1. Chitkara University,VLSI Centre of Excellence,Punjab,India

2. University Institute of Technology (UIT), HPU,Department of Electronic and Communication Engineering,Shimla,Himachal Pradesh,India

3. Chitkara University,Department of Electronics and Communication Engineering,Punjab,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10092281/10092284/10092338.pdf?arnumber=10092338

Reference21 articles.

1. Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

2. Digital circuit optimization using Pass Transistor Logic architectures

3. A 16 nm finfet circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance sram architecture;jeevan;Semiconductor Science and Technology,2022

4. Back to the Future: Digital Circuit Design in the FinFET Era

5. FDSTDL: Low‐power technique for FinFET domino circuits

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation on Traffic Light Controller Using ARTIX-7 FPGA Board;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

2. Comparative Analysis of Power, Temperature and Hardware Utilization on Implementation of 4-Bit Comparator;2023 2nd International Conference on Futuristic Technologies (INCOFT);2023-11-24

3. Comparative Analysis of FinFET and CMOS based Adiabatic ECRL Technique;2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS);2023-06-14

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