Scalable hardware-algorithms for binary prefix sums-Reference-Cited by-同舟云学术

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Scalable hardware-algorithms for binary prefix sums

Published:2000 Issue:8 Volume:11 Page:838-850
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Lin R.,Nakano K.,Olariu S.,Pinotti M.C.,Schwing J.L.,Zomaya A.Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/71/19004/00877941.pdf?arnumber=877941

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fast problem-size-independent parallel prefix circuits;Journal of Parallel and Distributed Computing;2009-04

2. Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2;ACM Transactions on Design Automation of Electronic Systems;2009-01

3. A Tiny Processing System for Education and Small Embedded Systems on the FPGAs;2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing;2008-12

4. Accelerating Montgomery Modulo Multiplication for Redundant Radix-64k Number System on the FPGA Using Dual-Port Block RAMs;2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing;2008-12

5. A NEW FM SCREENING METHOD TO GENERATE CLUSTER-DOT BINARY IMAGES USING THE LOCAL EXHAUSTIVE SEARCH WITH FPGA ACCELERATION;International Journal of Foundations of Computer Science;2008-12

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