Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Author:

Sechen C.

Publisher

IEEE

Cited by 31 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design Automation Algorithms for the NP-Separate VLSI Design Methodology;ACM Transactions on Design Automation of Electronic Systems;2022-06-06

2. Global and Detailed Placement;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022

3. Chip Planning;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022

4. How Secure Is Split Manufacturing in Preventing Hardware Trojan?;ACM Transactions on Design Automation of Electronic Systems;2020-03-17

5. A Reinforcement Learning-Based Framework for Solving Physical Design Routing Problem in the Absence of Large Test Sets;2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD);2019-09

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