Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware
Author:
Affiliation:
1. Kyushu Institute of Technology,Dept. of Electrical Enginnering and Electronics,Kitakyushu,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10371372/10371720/10371721.pdf?arnumber=10371721
Reference15 articles.
1. A Consideration to Develop a High-level Synthesizable Software Game Library
2. DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler
3. Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
4. AnyHLS: High-Level Synthesis With Partial Evaluation
5. CNN-Grinder: From Algorithmic to High-Level Synthesis descriptions of CNNs for Low-end-low-cost FPGA SoCs
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1. Performance variation caused by sprite drawing pattern for high-level synthesized sprite drawing hardware;Proceedings of the 2024 6th International Electronics Communication Conference;2024-07-19
2. An investigation of line and frame based descriptions on designing sprite drawing hardware in high-level synthesis;2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2023-12-18
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