A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS
Author:
Affiliation:
1. Texas A&M University,Analog and Mixed-Signal Center,College Station,TX,USA,77843
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9859262/9859267/09859536.pdf?arnumber=9859536
Reference6 articles.
1. A Low-Noise Design Technique for High-Speed CMOS Optical Receivers
2. A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling
3. A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS;zheng;IEEE CICC,2018
4. Gigahertz transresistance amplifiers in fine line NMOS
5. Low-power CMOS receivers for short reach optical communication
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1. Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07
2. A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer;Analog Integrated Circuits and Signal Processing;2024-02-03
3. A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-μmCMOS process;Integration;2024-01
4. A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04
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