The Need for 2-Phase Design Paradigms in High-Throughput GALS Network-On-Chip Architectures
Author:
Affiliation:
1. School of Science, Engineering and Technology, RMIT University,Ho Chi Minh City,Vietnam
2. School of Engineering, RMIT University,Melbourne,Australia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10013784/10013785/10013843.pdf?arnumber=10013843
Reference32 articles.
1. Asynchronous 2-Phase Level-Encoded Convention Logic (LCL)
2. Extended Boolean algebra for asynchronous quasi‐delay‐insensitive logic
3. High performance protocol converters for two phase quasi-delay insensitive system-level communication
4. Asynchronous interconnect for synchronous soc design
5. A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems
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