Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement-Reference-Cited by-同舟云学术

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Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Published:2013-02 Issue:2 Volume:48 Page:611-623
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yang Shu-Meng,Chang Meng-Fan,Chiang Chi-Chuang,Chen Ming-Pin,Yamauchi Hiroyuki

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6419809/06407148.pdf?arnumber=6407148

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM;IEICE Transactions on Electronics;2022-11-01

2. Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems;2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2020-08

3. A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications;IEEE Electron Device Letters;2018-08

4. A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme;IEEE Journal of Solid-State Circuits;2017-09

5. Design of High-density Mask ROM Based on Diode Cells;J ELECTRON INF TECHN;2017

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