A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission-Reference-Cited by-同舟云学术

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A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

Published:2012-12 Issue:12 Volume:47 Page:3249-3260
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Cui Delong,Raghavan Bharath,Singh Ullas,Vasani Anand,Huang Zhi,Pi Deyi,Khanpour Mehdi,Nazemi Ali,Maarefi Hassan,Zhang Wei,Ali Tamer,Huang Nick,Zhang Bo,Momtaz Afshin,Cao Jun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6392234/06327376.pdf?arnumber=6327376

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Electronic Dispersion Compensation Transceiver for 10- and 28-Gb/s Directly Modulated Lasers-Based Optical Links;IEEE Journal of Solid-State Circuits;2019-01

2. A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2018-04-30

3. A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS;IEEE Journal of Solid-State Circuits;2017-11

4. A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-07

5. An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-03

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