A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface-Reference-Cited by-同舟云学术

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A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

Published:2017-06 Issue:6 Volume:52 Page:1563-1575
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lim Hyun-Wook,Choi Sung-Won,Ahn Jeong-Keun,Min Woong-Ki,Lee Sang-Kyu,Baek Chang-Hoon,Lee Jae-Youl,Hwang Gyoo-Cheol,Jun Young-Hyun,Kong Bai-Sun^ORCID

Funder

Strategic Joint Project initiated by Samsung Electronics

Industrial Strategic Technology Development Program funded by the Ministry of Trade, Industry & Energy

Basic Research Program through the National Research Foundation of Korea funded by the Ministry of Education

IDEC, KAIST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7933283/07894188.pdf?arnumber=7894188

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

2. A High Speed and Low BER Dual-mode Adaptive Equalizer Using Hybrid Parallel DFE;IEICE Electronics Express;2024

3. A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer;IEEE Journal of Solid-State Circuits;2022-10

4. A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer;2021 IEEE Asian Solid-State Circuits Conference (A-SSCC);2021-11-07

5. A Power-and Area-Efficient DFE Receiver with Tap Coefficient-rotating Summer for IoT Applications;2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia);2021-11-01

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