A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache-Reference-Cited by-同舟云学术

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A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Published:2011-01 Issue:1 Volume:46 Page:64-75
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Barth John,Nair Kavita,Cao Nianzheng,Plass Don,Nelson Erik,Hwang Charlie,Fredeman Gregory,Sperling Michael,Mathews Abraham,Kirihata Toshiaki,Reohr William R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5673672/05643084.pdf?arnumber=5643084

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2. Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM;IEEE Transactions on Nanotechnology;2021

3. Ultimate-D/SRAMs/CAMs;TFET Integrated Circuits;2020-11-07

4. A Classification of Memory-Centric Computing;ACM Journal on Emerging Technologies in Computing Systems;2020-04-30

5. Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers;Journal of Physics D: Applied Physics;2019-09-26

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