A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/5556407/05556423.pdf?arnumber=5556423
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis;Journal of Low Power Electronics and Applications;2018-07-30
2. Voltage-tolerant circuit design for fully CMOS-compatible differential multiple-time programmable nonvolatile memories;Japanese Journal of Applied Physics;2017-03-15
3. High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-08
4. High-frequency level-up shifter based on 0.18 µm vertical metal–oxide–semiconductor field-effect transistors with 70% reduction of overshoot voltage above power supply voltage;Japanese Journal of Applied Physics;2015-03-12
5. Optical Cache Memory Peripheral Circuitry: Row and Column Address Selectors for Optical Static RAM Banks;Journal of Lightwave Technology;2013-12
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