NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator
Author:
Affiliation:
1. INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal
Funder
Fundação para a Ciência e a Tecnologia (FCT), Portugal
European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9809931/09763876.pdf?arnumber=9763876
Reference64 articles.
1. Speeding up the Number Theoretic Transform for Faster Ideal Lattice-Based Cryptography
2. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
3. Wimpy or brawny cores: A throughput perspective
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