BR-CIM: An Efficient Binary Representation Computation-In-Memory Design

Author:

Yue Zhiheng1ORCID,Wang Yabing1,Qin Yubin1ORCID,Liu Leibo1ORCID,Wei Shaojun1ORCID,Yin Shouyi1ORCID

Affiliation:

1. School of Integrated Circuits, the Beijing Innovation Center for Future Chip, and the Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China

Funder

NSFC

National Key Research and Development Program

Beijing Science and Technology Project

Beijing Advanced Innovation Center for Integrated Circuits

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Reference29 articles.

1. Binarized neural networks;hubara;Proc Adv Neural Inf Process Syst,2016

2. XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices

3. Structured binary neural networks for accurate image classification and semantic segmentation;zhuang;Proc Conf Comput Vis Pattern Recognit,2018

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2. DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

3. A 1–8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-03

5. SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11

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