Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories-Reference-Cited by-同舟云学术

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Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

Published:2020-06 Issue:6 Volume:67 Page:2103-2113
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Moon Seungsik^ORCID,Choe Jeongwon,Lee Youngjoo^ORCID

Funder

National Research Foundation Grant through the Korean Government

Samsung Electronics

IC Design Education Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9076766/09027117.pdf?arnumber=9027117

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems;IEEE Transactions on Industrial Informatics;2024-05

3. A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces;2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2022-06-13

4. High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

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