Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium

Author:

Gupta Naina1ORCID,Jati Arpan2ORCID,Chattopadhyay Anupam1ORCID,Jha Gautam3

Affiliation:

1. School of Computer Science and Engineering, NTU, Nanyang Ave, Singapore

2. School of Physical and Mathematical Sciences, NTU, Nanyang Ave, Singapore

3. Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India

Funder

NRF SOCure Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Reference31 articles.

1. Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

2. CRYSTALS-Dilithium: A Lattice-Based Digital Signature Scheme

3. A unified cryptoprocessor for lattice-based signature and key-exchange;mert;IEEE Trans Comput,2022

4. A compact and high-performance hardware architecture for CRYSTALS-Dilithium;zhao;IACR Trans Cryptograph Hardw Embedded Syst,2022

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes;Electronics;2024-08-23

2. IOSHA - An Enhanced Hash Function for Secure and Efficient Key Generation in CRYSTALS-Dilithium for IoT;2024 International Conference on Quantum Communications, Networking, and Computing (QCNC);2024-07-01

3. A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

4. Sparse Polynomial Multiplication-Based High-Performance Hardware Implementation for CRYSTALS-Dilithium;2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2024-05-06

5. Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-03

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