A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling
Author:
Affiliation:
1. Infinera Corporation, Ottawa, ON, Canada
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9763566/09715725.pdf?arnumber=9715725
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