Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits-Reference-Cited by-同舟云学术

Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits

Published:2022-11 Issue:11 Volume:69 Page:4367-4380
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Luo Yubiao¹,Wang Shiqing²,Zuo Pushen²,Sun Zhong³^ORCID,Huang Ru³

Affiliation:

1. School of Integrated Circuits, Peking University, Beijing, China

2. School of Integrated Circuits, Institute for Artificial Intelligence, Peking University, Beijing, China

3. Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Institute for Artificial Intelligence, Peking University, Beijing, China

Funder

National Key Research and Development Program of China

NSFC

111 Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/9929246/09865136.pdf?arnumber=9865136

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