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High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization

  • Published:2021-01 Issue:1 Volume:68 Page:250-263
  • ISSN:1549-8328
  • Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Yuan TianORCID,Liu WeiqiangORCID,Han JieORCID,Lombardi FabrizioORCID

Funder

National Natural Science Foundation of China

Six Talent Peaks Project in Jiangsu Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 55 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Survey on Neural Network Hardware Accelerators;IEEE Transactions on Artificial Intelligence;2024-08

2. MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

3. ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

4. Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

5. RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04
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