Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs-Reference-Cited by-同舟云学术

Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs

Published:2022-05 Issue:5 Volume:69 Page:1962-1975
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Mahdavi Mojtaba¹^ORCID,Weithoffer Stefan²^ORCID,Herrmann Matthias³^ORCID,Liu Liang¹^ORCID,Edfors Ove¹^ORCID,Wehn Norbert³^ORCID,Lentmaier Michael¹^ORCID

Affiliation:

1. Department of Electrical and Information Technology (EIT), Lund University, Lund, Sweden

2. Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France

3. Department of Electrical and Computer Engineering, Technical University of Kaiserslautern, Kaiserslautern, Germany

Funder

Ericsson Research Foundation, Sweden

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9763566/09721673.pdf?arnumber=9721673

Reference26 articles.

1. Advanced Hardware Architectures for Turbo Code Decoding Beyond 100 Gb/s

2. Fully Pipelined Iteration Unrolled Decoders the Road to TB/S Turbo Decoding

3. A 2.15 GBit/s turbo code decoder for LTE advanced base station applications;ilnseher;Proc 7th Int Symp Turbo Codes Iterative Inf Process (ISTC),2012

4. High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

5. Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems

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