A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS

Author:

Cao YuefengORCID,Zhang ShuminORCID,Zhang TianliORCID,Chen YongzhenORCID,Zhao YutongORCID,Chen ChixiaoORCID,Ye FanORCID,Ren JunyanORCID

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Dual-Mode Split-Based Calibration Technique for Time-Interleaved ADCs;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

2. Artificial Neural Network Based Calibration for a 12 b 250 MS/s Pipelined-SAR ADC With Ring Amplifier in 40-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. An Energy Efficient 7.59-ENOB 50 MS/s Flash-SAR ADC in 65-nm CMOS;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

4. A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost;Electronics Letters;2023-08

5. A non-pipelined ADC with a GM-R amplifier;Microelectronics Journal;2023-07

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