A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Ave, Singapore
2. Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA
Funder
Samsung Fund from Samsung Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10089883/10012044.pdf?arnumber=10012044
Reference40 articles.
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3. 15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
4. A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications
5. A 351 TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications;dong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020
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2. Configurable in-memory computing architecture based on dual-port SRAM;Microelectronics Journal;2024-05
3. A 1–8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04
4. An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01
5. A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024
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