Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips-Reference-Cited by-同舟云学术

Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips

Published:2023-06 Issue:6 Volume:70 Page:2271-2282
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Tao Tuomin¹^ORCID,Ma Hanzhi¹^ORCID,Li Da¹^ORCID,Li Yan²^ORCID,Tan Shurun¹^ORCID,Liu En-Xiao³^ORCID,Schutt-Aine Jose⁴,Li Er-Ping¹^ORCID

Affiliation:

1. Key Laboratory of Advanced Micro/Nano Electronic Devices and Smart Systems and Applications, College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China

2. Key Laboratory of Electromagnetic Wave Information Technology and Metrology, Jiliang University, Hangzhou, China

3. A*STAR Institute of High Performance Computing, Fusionopolis, Singapore

4. Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Champaign, IL, USA

Funder

National Natural Science Foundation of China

Zhejiang Laboratory Foundation of China

Zhejiang Provincial Natural Science Foundation of China

Start-Up Funds of Zhejiang University

Zhejiang University-Singapore University of Technology and Design (ZJU-SUTD) Innovation, Design and Entrepreneurship Alliance

Dynamic Research Enterprise for Multidisciplinary Engineering Sciences (DREMES) Seed Project of the Zhejiang University-University of Illinois at Urbana-Champaign (ZJU-UIUC) Joint Research Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10137339/10065570.pdf?arnumber=10065570

Reference33 articles.

1. Circuit Modeling for RRAM-Based Neuromorphic Chip Crossbar Array With and Without Write-Verify Scheme

2. Solving a classification task by spiking neurons with STDP and temporal coding

3. Design and Optimization of Non-volatile Capacitive Crossbar Array for In-Memory Computing

4. Fully hardware-implemented memristor convolutional neural network

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