Hardware evaluation of spike detection algorithms towards wireless brain machine interfaces
Author:
Affiliation:
1. Imperial College,Department of Electrical and Electronic Engineering,London,UK,SW7 2BT
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9948537/9948538/09948632.pdf?arnumber=9948632
Reference29 articles.
1. Numerical analysis of temperature elevation in the head due to power dissipation in a cortical implant
2. To sort or not to sort: the impact of spike-sorting on neural decoding performance
3. What limits the performance of current invasive brain machine interfaces?
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5. Compact standalone platform for neural recording with real-time spike sorting and data logging
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1. An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing;IEEE Journal of Solid-State Circuits;2023-11
2. A Clockless Robust Bionic Spike Detector for Implantable Brain-Computer Interfaces;2023 IEEE Biomedical Circuits and Systems Conference (BioCAS);2023-10-19
3. Calibration-Free and Hardware-Efficient Neural Spike Detection for Brain Machine Interfaces;IEEE Transactions on Biomedical Circuits and Systems;2023-08
4. NeuroBMI: A New Neuromorphic Implantable Wireless Brain Machine Interface with A 0.48 µW Event-Driven Noise-Tolerant Spike Detector;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11
5. Firing-rate-modulated spike detection and neural decoding co-design;Journal of Neural Engineering;2023-05-05
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