Quantitative analysis of very-low-voltage testing-Reference-Cited by-同舟云学术

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Quantitative analysis of very-low-voltage testing

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Container-title:Proceedings of 14th VLSI Test Symposium
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Author:

Chang J.T.-Y.,McCluskey E.J.

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx3/3739/10937/00510876.pdf?arnumber=510876

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts;2021 IEEE 39th VLSI Test Symposium (VTS);2021-04-25

3. Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling;Journal of Electronic Testing;2017-03-15

4. Demystifying Iddq Data With Process Variation for Automatic Chip Classification;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-06

5. Low VDD and body bias conditions for testing bridge defects in the presence of process variations;Microelectronics Journal;2015-05

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