On the design of self-testing checkers for modified Berger codes
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Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/7458/20291/00937835.pdf?arnumber=937835
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing;Scientific Programming;2018-06-07
2. Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-04
3. Monitoring Transient Errors in Sequential Circuits;16th Asian Test Symposium (ATS 2007);2007-10
4. Lowering power consumption in concurrent checkers via input ordering;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2004-11
5. Input ordering in concurrent checkers to reduce power consumption;17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.
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