A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting
Author:
Affiliation:
1. The University of Aizu,School of Computer Science and Engineering,Aizu-Wakamatsu,Japan
2. Tohoku University,Graduate School of Engineering,Sendai,Japan
3. Tohoku University,Research Institute of Electrical Communication,Sendai,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9691770/9691932/09691936.pdf?arnumber=9691936
Reference18 articles.
1. 33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications
2. A 47.14-$\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
3. Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting
4. Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting
5. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction
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